I²C
mode
I²C
mode (Inter IC Bus) is especially suitable when the microcontroller and
integrated circuit, which the microcontroller should exchange data with, are
within the same device. It is commonly about another microcontroller or
specialized, cheap integrated circuits belonging to the new generation of so
called "smart peripheral components" (memories, temperature sensors,
real-time clocks etc.)
Similar
to serial communication in SPI mode, data transfer in I²C mode is synchronous
and bidirectional. This time only two pins are used for data transfer. These
are the SDA (Serial Data) and SCL (Serial Clock) pins. The user must configure
these pins as inputs or outputs through the TRISC bits.
Perhaps
it is not directly visible. By observing particular rules (protocols), this
mode enables up to 122 different components to be simultaneously connected in a
simple way by using only two valuable I/O pins. Briefly, everything works as
follows: Clock necessary to synchronize the operation of both devices is always
generated by the master device (microcontroller) and its frequency directly
affects baud rate. There are protocols allowing maximum 3,4 MHz clock frequency
(so called high-speed I²C bus), but the clock frequency of the most frequently
used protocol is limited to 100 KHz. There is no limit in case of minimal
frequency.
When
master and slave components are synchronized by the clock, every
data exchange is always initialized by master. Once the MSSP module has been
enabled, it waits for a Start condition to occur. First the master device sends
the START bit (logic zero) through the SDA pin, then the 7-bit address of the
selected slave device, and finally, the bit which requires data write (0) or
read (1) to that device. Accordingly, following the start condition, the eight
bits are shifted into the SSPSR register. All slave devices share the same
transmission line and all will simultaneously receive the first byte, but only
one of them has the address to match.
 |
| Fig. 1 Master and Slave Configuration |
Once
the first byte has been sent (only 8-bit data are transmitted), master goes
into receive mode and waits for acknowledgment from the receive device that
address match has occurred. If the slave device sends acknowledge data bit (1),
data transfer will be continued until the master device (microcontroller) sends
the Stop bit.
This
is the simplest explanation of how two components communicate. If needed, this
microcontroller is able to control more complicated situations when 1024
different components, shared by several different master devices, are
connected. Such devices are rarely used in practice and there is no need to
discuss them at greater length.
 |
Fig. 2 Data Transfer
|
Figure below shows
the block diagram of the MSSP module in I²C mode
 |
Fig. 3 MSSP Block Diagram in I²C Mode
|
The MSSP module
uses six registers for I²C operation. Some of them are shown in figure above:
· SSPCON;
· SSPCON2;
· SSPSTAT;
· SSPBUF;
· SSPSR; and
· SSPADD.
SSPSTAT Register
 |
Fig. 4 SSPSTAT Register
|
SMP
Sample bit
SPI
master mode - This bit determines input data phase.
·
1 -
Logic state is read at end of data output time; and
·
0 -
Logic state is read in the middle of data output time.
SPI
slave mode This bit must be cleared when SPI is used in Slave mode.
I²C
mode (master or slave)
·
1 -
Slew rate control disabled for standard speed mode (100kHz); and
·
0 -
Slew rate control enabled for high speed mode (400kHz).
CKE
- Clock Edge Select bit
selects synchronization mode.
CKP
= 0:
·
1 -
Data is transmitted on rising edge of clock pulse (0 - 1); and
·
0 -
Data is transmitted on falling edge of clock pulse (1 - 0).
CKP
= 1:
·
1 -
Data is transmitted on falling edge of clock pulse (1 - 0); and
·
0 -
Data is transmitted on rising edge of clock pulse (0 - 1).
D/A
- Data/Address bit is
used in I²C mode only.
·
1 -
Indicates that the last byte received or transmitted was data; and
·
0 -
Indicates that the last byte received or transmitted was address.
P -
Stop bit is used in I²C
mode only.
·
1 -
STOP bit was detected last; and
·
0 -
STOP bit was not detected last.
S -
Start bit is used in I²C
mode only.
·
1 -
START bit was detected last; and
·
0 -
START bit was not detected last.
R/W
- Read Write bit is
used in I²C mode only. This bit holds the R/W bit information following the
last address match. This bit is only valid from the address match to the next
Start bit, Stop bit or not ACK bit.
In
I²C slave mode
·
1 -
Data read; and
·
0 -
Data write.
In
I²C master mode
·
1 -
Transmit is in progress; and
·
0 -
Transmit is not in progress.
UA
- Update Address bit is
used in 10-bit I²C mode only.
·
1 -
Indicates that it is necessary to update the address in the SSPADD register;
and
·
0 -
Address in the SSPADD register is correct and does not need to be updated.
BF Buffer Full Status bit
During
data receive (in SPI and I²C modes)
·
1 -
Receive complete. The SSPBUF register is full; and
·
0 -
Receive not complete. The SSPBUF register is empty.
During
data transmit (in I²C mode only)
·
1 -
Data transmit in progress (does not include the bits ACK and STOP); and
·
0 -
Data transmit complete (does not include the bits ACK and STOP).
SSPCON Register
 |
Fig. 5 SSPCON Register
|
WCOL
Write Collision Detect bit
· 1 - Collision detected. A write to the SSPBUF register was
attempted while the I²C conditions were not valid for a transmission to start;
and
· 0 - No collision.
SSPOV
Receive Overflow Indicator bit
· 1 - A new byte is received while the SSPSR register still
holds the previous data. Since there is no space for new data receive, one of
these two bytes must be cleared. In this case, data in SSPSR is lost; and
· 0 - Serial data is correctly received.
SSPEN
- Synchronous Serial Port Enable bit
determines the microcontroller pins function and initializes MSSP module:
In
SPI mode
· 1 - Enables MSSP module and configures pins SCK, SDO, SDI
and SS as the source of the serial port pins; and
· 0 - Disables MSSP module and configures these pins as I/O
port pins.
In
I²C mode
· 1 - Enables MSSP module and configures pins SDA and SCL as
the source of the serial port pins; and
· 0 - Disables MSSP module and configures these pins as I/O
port pins.
CKP
- Clock Polarity Select bit is not used in
I²C master mode.
In
SPI mode
· 1 - Idle state for clock is a high level; and
· 0 - Idle state for clock is a low level.
In
I²C slave mode
· 1 - Enables clock; and
· 0 - Holds clock low. Used to provide more time for data
stabilization.
SSPM3-SSPM0
- Synchronous Serial Port Mode Select bits.
SSP mode is determined by combining these bits:
SSPM3
|
SSPM2
|
SSPM1
|
SSPM0
|
Mode
|
0
|
0
|
0
|
0
|
SPI master mode,
clock = Fosc/4
|
0
|
0
|
0
|
1
|
SPI master mode,
clock = Fosc/16
|
0
|
0
|
1
|
0
|
SPI master mode,
clock = Fosc/64
|
0
|
0
|
1
|
1
|
SPI master mode,
clock = (output TMR)/2
|
0
|
1
|
0
|
0
|
SPI slave mode, SS
pin control enabled
|
0
|
1
|
0
|
1
|
SPI slave mode, SS
pin control disabled, SS can be used as I/O pin
|
0
|
1
|
1
|
0
|
I²C slave mode,
7-bit address used
|
0
|
1
|
1
|
1
|
I²C slave mode,
10-bit address used
|
1
|
0
|
0
|
0
|
I²C master mode,
clock = Fosc / [4(SSPAD+1)]
|
1
|
0
|
0
|
1
|
Mask used in I²C
slave mode
|
1
|
0
|
1
|
0
|
Not used
|
1
|
0
|
1
|
1
|
I²C controlled
master mode
|
1
|
1
|
0
|
0
|
Not used
|
1
|
1
|
0
|
1
|
Not used
|
1
|
1
|
1
|
0
|
I²C slave mode,
7-bit address used,START and STOP bits enable interrupt
|
1
|
1
|
1
|
1
|
I²C slave mode,
10-bit address used,START and STOP bits enable interrupt
|
Table 1 Synchronous Serial Port Mode Select Bits
SSPCON2 Register
 |
| Fig. 6 SSPCON2 Register |
GCEN
- General Call Enable bit
In
I²C slave mode only
· 1 - Enables interrupt when a general call address (0000h) is
received in the SSPSR; and
· 0 - General call address disabled.
ACKSTAT
- Acknowledge Status bit
In
I²C Master Transmit mode only
· 1 - Acknowledge was not received from slave; and
· 0 - Acknowledge was received from slave.
ACKDT
- Acknowledge data bit
In
I²C Master Receive mode only
· 1 - Not Acknowledge; and
· 0 - Acknowledge.
ACKEN
- Acknowledge condition Enable bit
In
I²C Master Receive mode
· 1 - Initiate acknowledge condition on SDA and SCL pins and
transmit ACKDT data bit. It is automatically cleared by hardware; and
· 0 - Acknowledge condition is not initiated.
RCEN
- Receive Enable bit
In
I²C Master mode only
· 1 - Enables data receive in I²C mode; and
· 0 - Receive disabled.
PEN
- STOP condition Enable bit
In
I²C Master mode only
· 1 - Initiates STOP condition on pins SDA and SCL.
Afterwards, this bit is automatically cleared by hardware; and
· 0 - STOP condition is not initiated.
RSEN
- Repeated START Condition Enabled bit
In
I²C master mode only
· 1 - Initiates START condition on pins SDA and SCL.
Afterwards, this bit is automatically cleared by hardware; and
· 0 - Repeated START condition is not initiated.
SEN
- START Condition Enabled/Stretch Enabled bit
In
I²C Master mode only
· 1 - Initiate START condition on pins SDA and SCL.
Afterwards, this bit is automatically cleared by hardware; and
· 0 - START condition is not initiated.
I²C
in Master Mode
The
most common case is when the microcontroller operates as a master and the
peripheral component as a slave. This is why this book covers just this mode.
It is also considered that the address consists of 7 bits and device contains
only one microcontroller (one master device).
In
order to enable MSSP module in this mode, it is necessary to do the following:
Set
baud rate (SSPADD register), turn off slew rate control (by setting the SMP bit
of the SSPSTAT register) and select master mode (SSPCON register). After the
preparation has been finished and module has been enabled (SSPCON register:
SSPEN bit), one should wait for internal electronics to signal that everything
is ready for data transmission, i.e. the SSPIF bit of the PIR1 register is set.
This bit should be cleared by software and after
that, the microcontroller is ready to start "communication" with
peripherals.
 |
Fig.7 I²C in Master Mode
|
Data
Transmission in I²C Master Mode
Each
clock condition on the SDA pin starts with logic zero (0) which appears upon
setting the SEN bit of the SSPCON2 register. Even enabled, the microcontroller
has to wait a certain time before it starts communication. It is the so called
"Start condition" during which internal preparations and checks are
performed. If all conditions are met, the SSPIF bit of the PIR1 is set and data
transfer starts as soon as the SSPBUF register is loaded.
Since
maximum 112 integrated circuits may simultaneously share the same transmission
line, the first data byte must contain address which matches only one slave
device. Each component has its own address listed in the proper data sheet. The
eighth bit of the first data byte specifies direction of data transmission, the
microcontroller is to send or receive data. In this case, it is all about data
receive and the eighth bit therefore is logic zero (0).
When
address match occurs, the microcontroller has to wait for the acknowledge data
bit. The slave device acknowledges address match by clearing the ASKSTAT bit of
the SSPCON2 register. If the match properly occurred, all bytes representing
data are transmitted in the same way.
Data
transmission ends by setting the SEN bit of the SSPCON2 register. The so called
STOP condition occurs, which enables the SDA pin to receive pulse condition:
Start - Address - Acknowledge - Data - Acknowledge ....Data - Acknowledge -
Stop!
Data
Reception in I²C Master Mode
Preparations
for data reception are similar to those for data transmission, with exception
that the last bit of the first sent byte (containing address) is logic one (1).
It specifies that master expects to receive data from addressed slave device.
With regard to the microcontroller, the following events occur:
After
internal preparations are finished and START bit is set, slave device starts
sending one byte at a time. These bytes are stored in the serial register
SSPSR. Each data is, after receiving the last eighth bit, loaded to the SSPBUF
register from where it can be read. By reading this register, the acknowledge
bit is automatically sent, which means that master device is ready to receive
new data.
At
the end, similar to data transmission, data reception ends by setting the STOP
bit:
 |
Fig. 10 Data Reception in I²C Master
Mode
|
Baud
Rate Generator
In
order to synchronize data transmission, all events taking place on the SDA pin
must be synchronized with the clock generated in master device. This clock is
generated by a simple oscillator whose frequency depends on the
microcontroller’s main oscillator frequency, value written to the SSPADD
register and the current SPI mode.
The clock frequency of the mode described in
this book depends on selected quartz crystal and the SPADD register. The
formula used to calculate it is shown in figure below.
 |
Fig. 11 Baud Rate Generator
|
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