PIC16C73/73A/74/74A Microcontroller Architecture



Central Processor Unit (CPU)

RISC Reduced Instruction Set Computer, gives the PIC16C7x two great advantages:

The CPU can recognizes only 35 simple instructions (In order to program some other microcontrollers it is necessary to know more than 200 instructions by heart).
The execution time is the same for all instructions except two and lasts 4 clock cycles (oscillator frequency is stabilized by a quartz crystal). The Jump and Branch instructions execution time is 2 clock cycles. It means that if the microcontroller’s operating speed is 20MHz, execution time of each instruction will be 200nS, i.e. the program will be executed at the speed of 5 million instructions per second!

Memory

This microcontroller has three types of memory- ROM, RAM and EEPROM. All of them will be separately discussed since each has specific functions, features and organization.

ROM Memory

ROM memory is used to permanently save the program being executed. This is why it is often called “program memory”. The PIC16C7X has 8Kb of ROM (in total of 8192 locations=8*1024). Since this ROM is made with FLASH technology, its contents can be changed by providing a special programming voltage (13V).



EEPROM Memory

Similar to program memory, the contents of EEPROM is permanently saved, even the power goes off. However, unlike ROM, the contents of the EEPROM can be changed during operation of the microcontroller. That is why this memory (256 locations) is a perfect one for permanently saving results created and used during the operation.

RAM Memory

This is the third and the most complex part of microcontroller memory. In this case, it consists of two parts: general-purpose registers and special-function registers (SFR).

Even though both groups of registers are cleared when power goes off and even though they are manufactured in the same way and act in the similar way, their functions do not have many things in common.



General-Purpose Registers

General-Purpose registers are used for storing temporary data and results created during operation. For example, if the program performs a counting (for example, counting products on the assembly line), it is necessary to have a register which stands for what we in everyday life call “sum”. Since the microcontroller is not creative at all, it is necessary to specify the address of some general purpose register and assign it a new function. A simple program to increment the value of this register by 1, after each product passes through a sensor, should be created.
Therefore, the microcontroller can execute that program because it now knows what and where the sum which must be incremented is. Similarly to this simple example, each program variable must be pre assigned some of general-purpose register.

SFR Registers

Special-Function registers are also RAM memory locations, but unlike general-purpose registers, their purpose is predetermined during manufacturing process and cannot be changed. Since their bits are physically connected to particular circuits on the chip (A/D converter, serial communication module, etc.), any change of their contents directly affects the operation of the microcontroller or some of its circuits. For example, by changing the TRISA register, the function of each port A pin can be changed in a way it acts as input or output. Another feature of these memory locations is that they have their names (registers and their bits), which considerably facilitates program writing. Since high-level programming language can use the list of all registers with their exact addresses, it is enough to specify the register’s name in order to read or change its contents.

RAM Memory Banks

The data memory is partitioned into four banks. Prior to accessing some register during program writing (in order to read or change its contents), it is necessary to select the bank which contains that register. Two bits of the STATUS register are used for bank selecting, which will be discussed later. In order to facilitate operation, the most commonly used SFRs have the same address in all banks which enables them to be easily accessed.






STACK

A part of the RAM used for the stack consists of eight 13-bit registers. Before the microcontroller starts to execute a subroutine (CALL instruction) or when an interrupt occurs, the address of first next instruction being currently executed is pushed onto the stack, i.e. onto one of its registers. In that way, upon subroutine or interrupt execution, the microcontroller knows from where to continue regular program execution. This address is cleared upon return to the main program because there is no need to save it any longer, and one location of the stack is automatically available for further use.
It is important to understand that data is always circularly pushed onto the stack. It means that after the stack has been pushed eight times, the ninth push overwrites the value that was stored with the first push. The tenth push overwrites the second push and so on. Data overwritten in this way is not recoverable. In addition, the programmer cannot access these registers for write or read and there is no Status bit to indicate stack overflow or stack underflow conditions. For that reason, one should take special care of it during program writing.

Interrupt System

The first thing that the microcontroller does when an interrupt request arrives is to execute the current instruction and then stop regular program execution. Immediately after that, the current program memory address is automatically pushed onto the stack and the default address (predefined by the manufacturer) is written to the program counter. That location from where the program continues execution is called the interrupt vector. For the PIC16C7X microcontroller, this address is 0004h. As seen in Fig. 1-7 below, the location containing interrupt vector is passed over during regular program execution.

Part of the program being activated when an interrupt request arrives is called the interrupt routine. Its first instruction is located at the interrupt vector. How long this subroutine will be and what it will be like depends on the skills of the programmer as well as the interrupt source itself. Some microcontrollers have more interrupt vectors (every interrupt request has its vector), but in this case there is only one. Consequently, the first part of the interrupt routine consists in interrupt source recognition.
Finally, when the interrupt source is recognized and interrupt routine is executed, the microcontroller reaches the RETFIE instruction, pops the address from the stack and continues program execution from where it left off.



The special function registers can be classified into two categories:

Core (CPU) registers - control and monitor operation and processes in the central processor. Even though there are only a few of them, the operation of the whole microcontroller depends on their contents.
Peripheral SFRs- control the operation of peripheral units (serial communication module, A/D converter etc.). Each of these registers is mainly specialized for one circuit and for that reason they will be described along with the circuit they are in control of.

The core (CPU) registers of the PIC16C7X microcontroller are described here. Since their bits control several different circuits within the chip, it is not possible to classify them into some special group. These bits are described along with the processes they control.

STATUS Register




The STATUS register contains: the arithmetic status of the W register, the RESET status and the bank select bits for data memory. One should be careful when writing a value to this register because if you do it wrong, the results may be different than expected. For example, if you try to clear all bits using the CLRF STATUS instruction, the result in the register will be 000xx1xx instead of the expected 00000000. Such errors occur because some of the bits of this register are set or cleared according to the hardware as well as because the bits 3 and 4 are readable only. For these reasons, if it is required to change its content (for example, to change active bank), it is recommended to use only instructions which do not affect any Status bits (C, DC and Z). 

IRP - Bit selects register bank. It is used for indirect addressing.
1 - Banks 0 and 1 are active (memory location 00h-FFh)
0 - Banks 2 and 3 are active (memory location 100h-1FFh)

RP1,RP0 - Bits select register bank. They are used for direct addressing.

RP1
RP0
Active Bank
0
0
Bank0
0
1
Bank1
1
0
Bank2
1
1
Bank3

TO - Time-out bit.
1 - After power-on or after executing CLRWDT instruction which resets watch-dog timer or SLEEP instruction which sets the microcontroller into low-consumption mode.
0 - After watch-dog timer time-out has occurred.
PD - Power-down bit.
1 - After power-on or after executing CLRWDT instruction which resets watch-dog timer.
0 - After executing SLEEP instruction which sets the microcontroller into low-consumption mode.
Z - Zero bit
1 - The result of an arithmetic or logic operation is zero.
0 - The result of an arithmetic or logic operation is different from zero.
DC - Digit carry/borrow bit is changed during addition and subtraction if an “overflow” or a “borrow” of the result occurs.
1 - A carry-out from the 4th low-order bit of the result has occurred.
0 - No carry-out from the 4th low-order bit of the result has occurred.
C - Carry/Borrow bit is changed during addition and subtraction if an “overflow” or a “borrow” of the result occurs, i.e. if the result is greater than 255 or less than 0.
1 - A carry-out from the most significant bit of the result has occurred.
0 - No carry-out from the most significant bit of the result has occurred

OPTION_REG Register





Interrupt System Registers

When an interrupt request arrives it does not mean that interrupt will automatically occur, because it must also be enabled by the user (from within the program). Because of that, there are special bits used to enable or disable interrupts. It is easy to recognize these bits by IE contained in their names (stands for Interrupt Enable). Besides, each interrupt is associated with another bit called the flag which indicates that interrupt request has arrived regardless of whether it is enabled or not. They are also easily recognizable by the last two letters contained in their names- IF (Interrupt Flag).



If the appropriate IE bit is not set (0), this event will be completely ignored. Otherwise, an interrupt occurs! In case several interrupt sources are enabled, it is necessary to detect the active one before the interrupt routine starts execution. Source detection is performed by checking flag bits.

GIE bit - enables all unmasked interrupts and disables all interrupts simultaneously.
PEIE bit - enables all unmasked peripheral interrupts and disables all peripheral interrupts (This does not concern Timer TMR0 and port B interrupt sources).
To enable interrupt caused by changing logic state on port B, it is necessary to enable it for each bit separately. In this case, bits of the IOCB register have the function to control IE bits.




INTCON Register

The INTCON register contains various enable and flag bits for TMR0 register overflow, PORTB change and external INT pin interrupts.





GIE - Global Interrupt Enable bit - controls all possible interrupt sources simultaneously.
1 - Enables all unmasked interrupts.
0 - Disables all interrupts.
PEIE - Peripheral Interrupt Enable bit acts similar to GIE, but controls interrupts enabled by peripherals. It means that it does not affect interrupts triggered by the timer TMR0 or by changing state on port B or RB0/INT pin.
1 - Enables all unmasked peripheral interrupts.
0 - Disables all peripheral interrupts.
T0IE - TMR0 Overflow Interrupt Enable bit controls interrupt enabled by TMR0 overflow.
1 - Enables the TMR0 interrupt.
0 - Disables the TMR0 interrupt.
INTE - RB0/INT External Interrupt Enable bit controls interrupt caused by changing logic state on pin RB0/IN (external interrupt).
1 - Enables the INT external interrupt.
0 - Disables the INT external interrupt.
RBIE - RB Port Change Interrupt Enable bit. When configured as inputs, port B pins may cause interrupt by changing their logic state (no matter whether it is highto- low transition or vice versa, fact that something is changed only matters). This bit determines whether interrupt is to occur or not.
1 - Enables the port B change interrupt.
0 - Disables the port B change interrupt.
T0IF - TMR0 Overflow Interrupt Flag bit registers the timer TMR0 register overflow, when counting starts from zero.
1 - TMR0 register has overflowed (bit must be cleared in software).
0 - TMR0 register has not overflowed.
INTF - RB0/INT External Interrupt Flag bit registers change of logic state on the RB0/INT pin.
1 - The INT external interrupt has occurred (must be cleared in software).
0 - The INT external interrupt has not occurred.
RBIF - RB Port Change Interrupt Flag bit registers change of logic state of some port B input pins.
1 - At least one of the port B general purpose I/O pins has changed state. Upon reading portB, RBIF (flag bit) must be cleared in software.

0 - None of the port B general purpose I/O pins has changed state.


PIE1 Register

The PIE1 register contains the peripheral interrupt enable bits.



ADIE - A/D Converter Interrupt Enable bit.
1 - Enables the ADC interrupt.
0 - Disables the ADC interrupt.
RCIE - EUSART Receive Interrupt Enable bit.
1 - Enables the EUSART receive interrupt.
0 - Disables the EUSART receive interrupt.
TXIE - EUSART Transmit Interrupt Enable bit.
1 - Enables the EUSART transmit interrupt.
0 - Disables the EUSART transmit interrupt.
SSPIE - Master Synchronous Serial Port (MSSP) Interrupt Enable bit - enables an interrupt request to be generated after each data transfer via synchronous serial communication module (SPI or I2C mode).
1 - Enables the MSSP interrupt.
0 - Disables the MSSP interrupt.
CCP1IE - CCP1 Interrupt Enable bit enables an interrupt request to be generated in CCP1 module used for PWM signal processing.
1 - Enables the CCP1 interrupt.
0 - Disables the CCP1 interrupt.
TMR2IE - TMR2 to PR2 Match Interrupt Enable bit
1 - Enables the TMR2 to PR2 match interrupt.
0 - Disables the TMR2 to PR2 match interrupt.
TMR1IE - TMR1 Overflow Interrupt Enable bit enables an interrupt request to be generated after each timer TMR1 register overflow, i.e. when the counting starts from zero.
1 - Enables the TMR1 overflow interrupt.
0 - Disables the TMR1 overflow interrupt.

PIE2 Register

The PIE2 Register also contains the various interrupt enable bits.



OSFIE - Oscillator Fail Interrupt Enable bit.
1 - Enables oscillator fail interrupt.
0 - Disables oscillator fail interrupt.
C2IE - Comparator C2 Interrupt Enable bit.
1 - Enables Comparator C2 interrupt.
0 - Disables Comparator C2 interrupt.
C1IE - Comparator C1 Interrupt Enable bit.
1 - Enables Comparator C1 interrupt.
0 - Disables Comparator C1 interrupt.
EEIE - EEPROM Write Operation Interrupt Enable bit.
1 - Enables EEPROM write operation interrupt.
0 - Disables EEPROM write operation interrupt.
BCLIE - Bus Collision Interrupt Enable bit.
1 - Enables bus collision interrupt.
0 - Disables bus collision interrupt.
ULPWUIE - Ultra Low-Power Wake-up Interrupt Enable bit.
1 - Enables Ultra Low-Power Wake-up interrupt.
0 - Disables Ultra Low-Power Wake-up interrupt.
CCP2IE - CCP2 Interrupt Enable bit.
1 - Enables CCP2 interrupt.
0 - Disables CCP2 interrupt.

PIR1 Register

The PIR1 register contains the interrupt flag bits.


ADIF - A/D Converter Interrupt Flag bit.
1 - A/D conversion is completed (bit must be cleared in software).
0 - A/D conversion is not completed or has not started.
RCIF - EUSART Receive Interrupt Flag bit.
1 - The EUSART receive buffer is full. Bit is cleared by reading the RCREG register.
0 - The EUSART receive buffer is not full.
TXIF - EUSART Transmit Interrupt Flag bit.
1 - The EUSART transmit buffer is empty. Bit is cleared by writing to the TXREG register.
0 - The EUSART transmit buffer is full.
SSPIF - Master Synchronous Serial Port (MSSP) Interrupt Flag bit.
1 - The MSSP interrupt condition during data transmit/receive has occurred. These conditions differ depending on MSSP operating mode (SPI or I2C) This bit must be cleared in software before returning from the interrupt service routine.
0 - No MSSP interrupt condition has occurred.
CCP1IF - CCP1 Interrupt Flag bit.
1 - CCP1 interrupt condition has occurred (CCP1 is unit for capturing, comparing and generating PWM signal). Depending on operating mode, capture or compare match has occurred. In both cases, bit must be cleared in software. This bit is not used in PWM mode.
0 - No CCP1 interrupt condition has occurred.
TMR2IF - Timer2 to PR2 Interrupt Flag bit
1 - TMR2 (8-bit register) to PR2 match has occurred. This bit must be cleared in software before returning from the interrupt service routine.
0 - No TMR2 to PR2 match has occurred.
TMR1IF - Timer1 Overflow Interrupt Flag bit
1 - The TMR1 register has overflowed. This bit must be cleared in software.
0 - The TMR1 register has not overflowed.

PIR2 Register

The PIR2 register contains the interrupt flag bits.



OSFIF - Oscillator Fail Interrupt Flag bit.
1 - System oscillator failed and clock input has changed to internal oscillator INTOSC. This bit must be cleared in software.
0 - System oscillator operates normally.
C2IF - Comparator C2 Interrupt Flag bit.
1 - Comparator C2 output has changed (bit C2OUT). This bit must be cleared in software.
0 - Comparator C2 output has not changed.
C1IF - Comparator C1 Interrupt Flag bit.
1 - Comparator C1 output has changed (bit C1OUT). This bit must be cleared in software.
0 - Comparator C1 output has not changed.
EEIF - EE Write Operation Interrupt Flag bit.
1 - EEPROM write completed. This bit must be cleared in software.
0 - EEPROM write is not completed or has not started.
BCLIF - Bus Collision Interrupt Flag bit.
1 - A bus collision has occurred in the MSSP when configured for I2C Master mode. This bit must be cleared in software.
0 - No bus collision has occurred.
ULPWUIF - Ultra Low-power Wake-up Interrupt Flag bit.
1 - Wake-up condition has occurred. This bit must be cleared in software.
0 - No Wake-up condition has occurred.
CCP2IF - CCP2 Interrupt Flag bit.
1 - CCP2 interrupt condition has occurred (unit for capturing, comparing and generating PWM signal). Depending on operating mode, capture or compare match has occurred. In both cases, the bit must be cleared in software. This bit is not used in PWM mode.
0 - No CCP2 interrupt condition has occurred.

PCON register

The PCON register contains only two flag bits used to differentiate between a: power-on reset, brown-out reset, Watchdog Timer Reset and external reset (through MCLR pin).



ULPWUE - Ultra Low-Power Wake-up Enable bit
1 - Ultra Low-Power Wake-up enabled.
0 - Ultra Low-Power Wake-up disabled.
SBOREN - Software BOR Enable bit
1 - Brown-out Reset enabled.
0 - Brown-out Reset disabled.
POR - Power-on Reset Status bit
1 - No Power-on reset has occurred.
0 - Power-on reset has occurred. This bit must be set in software after a Power-on Reset occurs.
BOR - Brown-out Reset Status bit
1 - No Brown-out reset has occurred.
0 - Brown-out reset has occurred. This bit must be set in software after a Brown-out Reset occurs.




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