8051 Architecture - Features and Memory organization

8051 is based on the CISC architecture (Complex Instruction Set Computer) . Let us see the detailed architecture of 8051. Refer the video tutorial given below for the detailed explanation.

Features of 8051

  • 8bit CPU
  • Instruction Set of 111 operations which includes multiplication and division
  • 64K program memory address space is the maximum possible but usually it 4K
  • 64K data memory address space at the max but usually 128 bytes
  • Two 16 bit timers and counters
  • Full duplex serial port
  • On chip clock oscillator 
  • In general program is stored in ROM i.e., 4KB of onchip program memory. Process 128 bytes of internal data memory.
  • 3.5MHz to 24MHz is the range of oscillator clock frequency
8051 is a 8 bit micro controller. It has 3 IO banks i.e, PO, P1, P2, P3. In addition 16bit register DPTR to address the external data memory. One of the most frequently used register is accumulator. Almost all the arithmetic operations and data processed with the external data memory through accumulator. Register 'B' is involved in multiplication and division.

PSW(Program Status Word) is a 8bit register. PSW contains few flags i.e., Carry, Overflow

SP(Stack pointer) is related to stack operations and it is incremented before data is stored. Stack may reside anywhere in the internal RAM. Stack is initialized at 07h after reset. 07h is the address of stack. So stack will begin at 08h.

DPTR is a 16 bit register. Viewed as DPH and DPL. Common access to external data memory is based on this DPTR.

Program Counter addresses the instructions in the program memory as usual. Amount and type of the program memory varies with version. All the micro controller process atleast 128 bytes of internal memory. 

On chip Peripherals Consist of 
  • 4 parallel ports (P0 to P3)
  • One Serial port
  • Timer and counter
  • An interrupt unit
All the 4 ports are built from output registers and buffers (P0-B through P3-B). P0 and P2 only can be iterfaced with external memory. P3 is also a multi functional (Serial port, timer, counter). It has On chip oscillators.

Memory Organization

Memory organization is on two ports i.e., Program memory (4KB) and Data memory (128 bytes). Data memory is GPR and SFR. Memory can also divided to 4 separate address space. 
Program memory is the first address space (64K long i.e can be 4k, 8k, and more)

On Reset CPU begins execution from 0000h. All port pins goes to high on reset so it will be default in input mode.
How many interrupt sources are there in 8051?
  • INT0
  • INT1
  • TMR0
  • TMR1
  • Serial communication ( Rx, Tx)
All are having independent. Vector location of serial communication is same. All the interrupts are in fixed different location in memory. On interrupt service, Interrupt service routine runs. If interrupt is not used, service location is available as general purpose program memory. Interrupt service locations are spaced by 8 byte interval.

Micro controller executes instructions either from it or from external memory. When EA pin is connected to VCC then it selects on chip memory. When it is connected to ground then external memory is selected.

External Data Memory is next second memory. Program can access upto 64KB of data memory. Memory is addressed individually( DPTR, R0 or R1)

Internal Data Memory 256 bytes. It is divided to two blocks. 128 bytes for general purpose RAM (00 to 7Fh). Another 128 bytes (80h to FFh), the SFR area. Thus A, B, PSN, SP and DPTR plus all other. Control and stack register are viewed as internal data memory. SFR organized as an extension of internal RAM. 

8051 integrates peripheral devices these need control and status register. Lowest 32 bytes are grounded into 4 banks of 8 register each (R0 to R7).  

PSW performs both control and status function.2 bits in PSW selects banks in use.

Program counter address range - 0000h to FFFFh

P0 address - 00h to 07h

P1 address - 08h to 0Fh

P2 address - 10h to 17h

P3 address - 18h to 1Fh

In 8051 P0 port does not have internal pull up so there is a need for external pull up. P1,P2,P3 has internal pull up so the external pull up does not required for this.