ARi Interview Questions on Embedded C, C++, RTOS

The following questions are ARi embedded c interview questions on C, Embedded, I2C, RTOS, UART, RS232, RS485

1) What is the output of the following C Program?
int main()
   char ch = 256;
   return 0;

Answer : 0

2) What is the output of the following C Program?
int main()
   int a[3][3] = {{1,2,3},{4,5,6},{7,8,9}};
   return 0;
Answer : 7

3) What will happen when the program is compiled?
int main()
   int a[5];
   int b = a[6];
   return 0;
Answer: Program will compile successfully b is junk value

4) Difference between Structure and Union ?

5) How will you define Enum? and explain about it?

6) What is the output of the following program?
int main()
   extern int a;
   return 0;
Answer: Program will not compile it will throw the undefined reference to `a' error.

7) Explain about Dynamic Memory Allocation?

8) Where is local, static, global variables are stored? and what is Bss ?

Answer: Refer this URL

9) Explain about static variable ?

10) What is the Compilation process ?

11) What is the difference between RS232 and Rs485

12) What is I2C Start bit and Stop bit ?

Answer: Refer this URL

13) Explain about I2C Arbitration ?

Answer: Refer this URL

14) Explain about I2C Clock stretching?

Answer: Refer this URL

15) Difference between NAND Flash and NOR Flash ? ( Which one is fast and more )

16) How do you vary the duty cycle of the PWM ?

17) Can we change the PWM duty cycle in runtime ?

18) Do you know about CAN ?

19) Did you use multi master I2C in your project ?

20) Why RS485 is less noise ?

21) Why Pullup resistors are needed in I2C lines SCL and SCK ?

Answer: Refer this URL

22) How do you prioritize tasks in RTOS in you project ? 

Post your doubts in the comment section

I2C Bus Communication Protocol Tutorial with Example

What is I2C:

- Inter Integrated Circuit
- Bidirectional Data Transfer
- Half duplex (have only one data line)
- Synchronous bus so data is clocked with clock signal
- Clock is controlled when data line is changed

Speed of I2C:

low (under 100 kbps)
Fast (400 kbps)
high speed (3.4 mbps) I2C V2.0
2 wire communication :
Vtg high = 1, low = 0

when SCL = 1 data is a valid data, when SCL = 0 data changes
Basic protocol is master slave protocol
- Master controls the clock
- Slave device may hold the clock low to prevent data transfer
- no data transfer is present when clock is low
- It is a kind of wired and connection
- need to put pullup resistor
- default it is a open-drain or open-collector, so that adding pull up resistor is necessary so that it will have only two states that is 1.floating high and low
- Default state is high when no device is pulling it low

Packet format:

Start condition:

SDA changes High to Low when SCL is High

Stop Condition:

SDA changes Low to High when SCL is High

Repeated Start:

Incase of repeated start START condition is generated instead of STOP after a frame.

Data Transfer:

It is byte oriented (8bit)
Ack transmited by recepient of the data
MSB first
First byte is address
First byte is transmitted by master and addressed slave is the recepient
Next byte is based on the last bit (R/W)
7bit address
1 bit R/W
0 - master write
1 - master receive

9th Pulse ACK

 ACK => SDA - low
maste only generates clock and slave pulls low the SDA line

Full I2C Data transfer

I2C Multi Master:

It is a multi master bus
So bus arbitration is required
When two device tries to drive SDA to different value
It is necessary to be sure that is not interfiering with another message
If a device is trying to send logic one but hears logic 0, it immediately stops transmission and gives the other sender priority
Synch needed in SCL


Good for comm in On-board devices
Easy to link multiple devices because of addressing scheme
Cost and complexity do not scale up with the num of devices


The complexity of supporting software components can be higher than that of scheme(EX. SPI - No need of address in SPI)

Video Tutorail

What are hardware interrupts handled ?

When a device asserts its interrupt request signal, it must be processed in an orderly fashion. All CPUs, and many devices, have some mechanism for enabling/disabling interrupt recognition and processing: 

At the device level, there is usually an interrupt control register with bits to enable or disable the interrupts that device can generate. At the CPU level, a global mechanism functions to inhibit/enable (often called the global interrupt enable) recognition of interrupts. 

Systems with multiple interrupt inputs provide the ability to mask (inhibit) interrupt requests individually and/or on a priority basis. This capability may be built into the CPU or provided by an external interrupt controller. Typically, there is one or more interrupting mask registers, with individual bits allowing or inhibiting individual interrupt sources. 

There is often also one non-Maskable interrupt input to the CPU that is used to signal important conditions such as pending power fail, reset button pressed, or watchdog timer expiration. 

Figure 1 shows an interrupt controller, two devices capable of producing interrupts, a processor, and the interrupt-related paths among them. The interrupt controller multiplexes multiple input requests into one output. It shows which inputs are active and allows individual inputs to be masked. Alternatively, it prioritizes the inputs, shows the highest active input, and provides a mask for inputs below a given level. The processor status register has a global interrupt enable flag bit. In addition, a watchdog timer is connected to the non-Maskable interrupt input. 

The interrupt software associated with a specific device is known as its interrupt service routine (ISR), or handler.

Count the number of bits set in a integer

How to Check number of Bits set in a number(integer) ?

   ->Whenever a number increases by one the  LSB changes
   ->By using this technique we can easily find the number of bits set in a integer
   ->we can use, n &= (n-1) to find the number of bits set in a integer. Lets go to the program

C or C++ Program

count = 0;
   n &= (n-1);

Let us understand this Program with the help of number n = 52

count = 0

n = 52(0011 0100) & 51 (0011 0011) = 48(0011 0000)

count = 1

n = 48(0011 0000) & 47 (0010 1111) = 32(0010 0000)

count = 2

n = 32(0010 0000) & 31 (0001 1111) = 0

count = 3

Video Tutorial