What are hardware interrupts handled ?

When a device asserts its interrupt request signal, it must be processed in an orderly fashion. All CPUs, and many devices, have some mechanism for enabling/disabling interrupt recognition and processing: 

At the device level, there is usually an interrupt control register with bits to enable or disable the interrupts that device can generate. At the CPU level, a global mechanism functions to inhibit/enable (often called the global interrupt enable) recognition of interrupts. 

Systems with multiple interrupt inputs provide the ability to mask (inhibit) interrupt requests individually and/or on a priority basis. This capability may be built into the CPU or provided by an external interrupt controller. Typically, there is one or more interrupting mask registers, with individual bits allowing or inhibiting individual interrupt sources. 

There is often also one non-Maskable interrupt input to the CPU that is used to signal important conditions such as pending power fail, reset button pressed, or watchdog timer expiration. 

Figure 1 shows an interrupt controller, two devices capable of producing interrupts, a processor, and the interrupt-related paths among them. The interrupt controller multiplexes multiple input requests into one output. It shows which inputs are active and allows individual inputs to be masked. Alternatively, it prioritizes the inputs, shows the highest active input, and provides a mask for inputs below a given level. The processor status register has a global interrupt enable flag bit. In addition, a watchdog timer is connected to the non-Maskable interrupt input. 

The interrupt software associated with a specific device is known as its interrupt service routine (ISR), or handler.

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