I2C bus arbitration

We strongly recommed you to see the previous tutorial to understand the basics of I2C bus communication.

Lets move to I2C bus arbitration

I2C is designed for multi master purpose. So that in a single bus more than 1 masters can be connected.


Consider a scenario when both the masters (Master1 and Master2) start the communication at the same time !!!?? 

In this condition only the bus arbitration occurs.

If Master1 started the communication by pulling the clock low then the Master2 cannot able to control the clock untill the SCL is released by the Master1 (Master2 is considered as a slave in this condition). After the stop bit is observed by the Maste2 then it will start the communication.

The physical setup of the I2C bus helps the Master2 not to disturb the communication when the Master1 is communicating.



As the structure of I2C bus is wired AND condition if one line is pulled low then the line stays low.

when the Master2 changes the line to high the the line must go high, If not then the bus is occupied by the some other device which puts the line to low such as Master1 here.




Master2 will not get it's the data on the bus as long as there is no stop sequence. It will not touch the line and it leaves the SCL, SDA.



If the master cannot make the data line to go high, then it looses the arbitration and needs to back of and wait untill the stop sequence is seen.



Later it can check the line and make attempt when the line is free.

Let us take a small example where the Maste1 and Master2 wants to communicate with the same Slave (addr: 1111001). Master1 wants to write data 01010101 and Master2 wants to write data 01101110 to the slave.

The slave acknowlendges it and so for both the masters are in the impression that it owns the bus because so for they have transmistted same data on the bus.



Now, each master wants to transmit it's own data to the slave.
Master1 - 010 and Master2 - 011   what will go in the bus 0 or 1 ???

The moment when the data does not math Maste2 arbitration will be lost and it backs off because Master2 tries the Move the SDA high the data on the SDA remains low as it is a wired AND configuration (as Master1 already occupies it).



The Master2 does not get its data on the bus as long as there has been no STOP sequence presense on the bus till then it wont touch the bus.

This is how the I2C bus arbitration works.

Video




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